1. Field of the Invention
The invention relates to a phase-locked-loop circuit for deriving, from a sequence of samples of a band-limited data signal, the phase of the data signal at the corresponding sampling instants, the phase-locked-loop circuit comprising signal-generating, means for generating in synchronism with the samples, a sequence of phase values characterizing a periodic signal which varies as a substantially linear function of time between two constant limit values with a frequency which proportional to a control value; means for deriving interpolation values from the samples by interpolation, the interpolation values indicating the relative positions with respect to the sampling instants of the instants at which the data signal crosses a detection-level; phase-comparison means for deriving from the phase values, and the interpolation values a difference value which is indicative of the difference between the phase represented by the phase value and the actual phase of the data signal; and control means for controlling the signal-generating means depending on the difference value in such a way that the phase indicated by the phase value is maintained substantially equal to the actual phase of the data signal.
The invention further relates to a bit-detection arrangement for converting the sequence of samples into a binary signal made up of bit cells, this bit-detection arrangement comprising such a phase-locked-loop circuit.
2. Description of Related Art
Such circuits are known from European Patent Application EP 0,109,837. In the known phase-locked-loop circuit, the signal-generating means for generating the sequence of phase values comprise a discrete-time oscillator, comprising a digital summing circuit having a limited summing range, the pulse value stored in the summing circuit being adapted by means of the control value. The range of the summing circuit corresponds to 360.degree. and the control value is constant and corresponds to 180.degree.. The sampling rate is substantially equal to twice the bit rate of the data signal, so that the periodic signal characterized by the phase value has a frequency substantially equal to the bit rate. Since the phase of the data signal at the instants of crossing of the detection-level is known (zero), the difference between the actual phase and the phase represented by the phase value can be determined after every detection-level crossing. After the difference has been determined, the phase value is adapted depending on this difference in such a way that after adaptation, the phase represented by the phase value substantially corresponds to the actual phase. In this way the periodic signal characterized by the phase values and the data signal are locked in phase, so that at the sampling instants between the detection-level crossings, the phase value supplied by the discrete-time oscillator is always representative of the phase of the data signal. Each time that the phase value has exceeded a value corresponding to the phase "0", a bit-detection circuit detects a bit having a logic value dictated by the sign of the last sample.
This phase-locked-loop circuit and bit-detection circuit can be constructed entirely by means of digital elements, which has the advantage that these circuits together with the digital circuits for processing the information, for example decoding circuits and error-correction circuits, can be integrated simply on one chip.
However, the known circuits have the disadvantage that for a reliable bit detection, the bit rate should be substantially equal to half the sampling rate. If the bit rate deviates from this value, the phase shift between two successive samples no longer corresponds to 180.degree., so that the phase as represented by the phase value will deviate increasingly from the actual phase as the time interval between successive detection-level crossing increases, which may lead to erroneous bit detections.